Considering a programmable logic device (PLD) as one example of a programmable integrated circuit device, as applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals (such as by Finite Impulse Response (FIR) filtering). Such blocks are also frequently referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication results.
For example, PLDs sold by Altera Corporation, of San Jose, Calif., as part of the STRATIX®, ARRIA®, CYCLONE® and HARDCOPY® families include DSP blocks, each of which includes one or more multipliers. Each of those DSP blocks also includes one or more adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components of the block to be configured in different ways. In addition, those DSP blocks can be configured for operation at different precisions.
Such blocks typically have included direct connections that allow certain operations to be performed using only a chain or cascade including multiple ones of such blocks, while other operations cannot be completed without routing outputs from one of such blocks through the general purpose logic and interconnect of the programmable device before entering a subsequent one of such blocks.